User Guide
Page 58
...Serial Initialization Packet (SIP). The minimum assertion for the clock multiplier that are synchronous to 2.0 milliseconds. 46 Signal and Power-Up Requirements Chapter 8 Refer to AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902 for the processor, Northbridge, and PCI of the AMD Athlon... system bus for PCI RESET# is the same as PCI RESET#. Preliminary Information AMD Athlon™ XP Processor Model 6 ...
...Serial Initialization Packet (SIP). The minimum assertion for the clock multiplier that are synchronous to 2.0 milliseconds. 46 Signal and Power-Up Requirements Chapter 8 Refer to AMD Athlon™ and AMD Duron™ System Bus Specification, order# 21902 for the processor, Northbridge, and PCI of the AMD Athlon... system bus for PCI RESET# is the same as PCI RESET#. Preliminary Information AMD Athlon™ XP Processor Model 6 ...
User Guide
Page 82
... for more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656. The FID[3:0]signals must not be the same. 2. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002... FID[3:0] Pins FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are valid after PWROK is asserted. Table 21. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 12.5x or greater to determine the SIP (Serialization...
... for more information, refer to the AMD Athlon™ and AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656. The FID[3:0]signals must not be the same. 2. Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet 24309E-March 2002... FID[3:0] Pins FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are valid after PWROK is asserted. Table 21. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 12.5x or greater to determine the SIP (Serialization...
User Guide
Page 93
... Synchronous Direct Random Access Memory SIMD Single Instruction Multiple Data SIP Serial Initialization Packet SMbus System Management Bus SPD Serial Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory 81 24309E-March 2002 Appendix A Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet Table 24.
... Synchronous Direct Random Access Memory SIMD Single Instruction Multiple Data SIP Serial Initialization Packet SMbus System Management Bus SPD Serial Presence Detect SRAM Synchronous Random Access Memory SROM Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory 81 24309E-March 2002 Appendix A Preliminary Information AMD Athlon™ XP Processor Model 6 Data Sheet Table 24.