Data Sheet
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...-Up Requirements 43 Signal Sequence and Timing Description 43 Clock Multiplier Selection (FID[3:0 46 9.2 Processor Warm Reset Requirements 46 Northbridge Reset Pins 46 10 Mechanical Data 47 10.1 Die Loading 47 10.2 AMD Athlon XP Processor Model 10 Part Number 27488 OPGA Package Dimensions 48 10.3 AMD Athlon XP Processor Model 10 Part Number 27493 OPGA Package Dimensions 50 11...
...-Up Requirements 43 Signal Sequence and Timing Description 43 Clock Multiplier Selection (FID[3:0 46 9.2 Processor Warm Reset Requirements 46 Northbridge Reset Pins 46 10 Mechanical Data 47 10.1 Die Loading 47 10.2 AMD Athlon XP Processor Model 10 Part Number 27488 OPGA Package Dimensions 48 10.3 AMD Athlon XP Processor Model 10 Part Number 27493 OPGA Package Dimensions 50 11...
Data Sheet
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Table 30. Table 28. Table 31. FID[3:0] Clock Multiplier Encodings 74 Front-Side Bus Sense Truth Table 75 VID[4:0] Code to Voltage Definition 78 Constants and Variables for the Ideal Diode Equation 81 Constants and Variables Used in Temperature Offset Equations 82 Abbreviations 87 Acronyms 88 x List of Tables Table 29. Table 26. Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 Table 25. Table 27.
Table 30. Table 28. Table 31. FID[3:0] Clock Multiplier Encodings 74 Front-Side Bus Sense Truth Table 75 VID[4:0] Code to Voltage Definition 78 Constants and Variables for the Ideal Diode Equation 81 Constants and Variables Used in Temperature Offset Equations 82 Abbreviations 87 Acronyms 88 x List of Tables Table 29. Table 26. Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 Table 25. Table 27.
Data Sheet
Page 56
...as dictated by the VID[4:0] pins driven by a ring oscillator. The processor core voltage, VCC_CORE, must be within specification. When PWROK is an output of PWROK. Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 Power-Up Timing Requirements. In practice... PWROK is powered by VCCA. The reference system 44 Signal and Power-Up Requirements Chapter 9 The AMD Athlon XP processor model 10 does not set the correct clock multiplier if PWROK is asserted. VCCA must be asserted at least five microseconds before PWROK is recommended that the...
...as dictated by the VID[4:0] pins driven by a ring oscillator. The processor core voltage, VCC_CORE, must be within specification. When PWROK is an output of PWROK. Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 Power-Up Timing Requirements. In practice... PWROK is powered by VCCA. The reference system 44 Signal and Power-Up Requirements Chapter 9 The AMD Athlon XP processor model 10 does not set the correct clock multiplier if PWROK is asserted. VCCA must be asserted at least five microseconds before PWROK is recommended that the...
Data Sheet
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... are synchronous to determine the correct serial initialization packet (SIP). Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 Clock Multiplier Selection (FID[3:0]) The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to SYSCLK. This protocol uses the PROCRDY, CONNECT, and CLKFWDRST signals...
... are synchronous to determine the correct serial initialization packet (SIP). Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 Clock Multiplier Selection (FID[3:0]) The chipset samples the FID[3:0] signals in a chipset-specific manner from the processor and uses this information to SYSCLK. This protocol uses the PROCRDY, CONNECT, and CLKFWDRST signals...
Data Sheet
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...about Serialization Initialization Packets and SIP protocol. The FID[3:0] signals are open -drain and 2.5-V tolerant. FID[3:0] Clock Multiplier Encodings FID[3:0]2 Processor Clock to the processor, do not pull these Pin Descriptions Chapter 11 This CLK_Ctl setting is asserted. The FID[3:0]signals must not be...information, refer to be sampled until they become valid. BIOS initializes the CLK_Ctl MSR during the POST routine. Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 FID[3:0] Pins 74 FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0]...
...about Serialization Initialization Packets and SIP protocol. The FID[3:0] signals are open -drain and 2.5-V tolerant. FID[3:0] Clock Multiplier Encodings FID[3:0]2 Processor Clock to the processor, do not pull these Pin Descriptions Chapter 11 This CLK_Ctl setting is asserted. The FID[3:0]signals must not be...information, refer to be sampled until they become valid. BIOS initializes the CLK_Ctl MSR during the POST routine. Preliminary Information AMD Athlon™ XP Processor Model 10 Data Sheet 26237C-May 2003 FID[3:0] Pins 74 FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0]...