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Popular Intel I3-530 Manual Pages
Specifications - Page 2
....
2 Specification Update Intel may also require modifications of implementation of any features or instructions marked "reserved" or "undefined." Intel Turbo Boost Technology performance varies depending on request. Consult with your hardware and software configurations. For more information.
See http://www.intel.com/products/processor_number for details.
Setup...
Specifications - Page 5
... 2010
January 2011
5 Specification Update Added Errataum AAU92.
Corrected Extended Model and Model Number register values in error;
Revision History
Revision
Description
-001 -002
-003 -004 -005 -006
Initial Release
Added Errata AAU85-AAU87. Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor.
Added...
Specifications - Page 6
...IA-32 Architectures Software Developer's Manual, Volume 2B: Instruction Set Reference Manual N-Z Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide Intel® 64 and IA-32 Intel Architecture Optimization Reference Manual Intel® 64 and IA...
Specifications - Page 15
...SLBY2
i5-650 i3-550 i3-560
SLBMQ i3-540
C-2
20652h
3.20 / 1333 / 733
K-0
20655h
3.20 / 1333 / 733
K-0
20655h 3.33 / 1333 / 733
C-2
20652h 3.06 / 1333 / 733
Max Intel® Turbo Boost Technology Frequency
(GHz)2
2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60
2 core: 3.33 1 core: 3.46
2 core: 3.33 1 core: 3.46
N/A
N/A
N/A
Shared...
Specifications - Page 16
...IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled.
6. Intel® Virtualization Technology for 2 or 1 cores active
respectively.
3. Intel SSE4.1 and SSE4.2 enabled.
9.
This processor has TDP of 2)
S-Spec Number
Processor Number
Stepping
Processor Signature
Core Frequency (GHz) /
DDR3 (MHz) / Integrated Graphics Frequency
SLBLR i3-530
C-2
20652h 2.93...
Specifications - Page 18
...has either CR0.EM=1 (Emulation bit set , a MOVD/MOVQ with MMX/XMM register operands may be serviced before getting the DNA exception. Performance Monitor SSE Retired Instructions May Return Incorrect Values
Problem:
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is entered.
• If an instruction that performs a memory load causes a code segment limit violation.
• If...
Specifications - Page 21
... of Changes.
A DTLB error is decoded. Workaround: None identified. Status:
For the steppings affected, see the Summary Tables of Changes.
21 Specification Update
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted
Problem:
When the processor encounters an instruction that is greater than 15 bytes in length can incorrectly set the Overflow (bit...
Specifications - Page 24
... Architectures Software Developer's Manual Volume 3A: System Programming Guide, the ratio of debug tools should be a mismatched Stack Segment and Stack Pointer on the next clock.
If MOV SS/POP SS is not followed by an Instruction That Signals a Floating Point Exception
Problem:
A MOV SS/POP SS instruction should reflect actual performance while TM1 or on...
Specifications - Page 25
.... Workaround: Software should not be taken on the maximum core P-state. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is no Interrupt Service
Routine (ISR) set in the in its TCC activation temperature again.
Status:
For...
Specifications - Page 27
...core servicing...event.
Intel has...Problem:
If any commercially-available software/system. Specifically, return from an unexpected code address. Infinite Stream of the expected one when the processor returns to 0:
• A non-maskable interrupt (NMI);
• A machine-check exception (#MC);
• A page fault (#PF) during instruction... Changes.
27 Specification Update or
•...
Specifications - Page 28
.... Status:
For the steppings affected, see the Summary Tables of Changes.
28 Specification Update However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from the same or lower priority level will be Sent if Software Enters Core C6 During an Interrupt Service Routine
Problem:
If core C6 is written and further interrupts from counting during SMM...
Specifications - Page 30
... affected, see the Summary Tables of Changes.
30 Specification Update AAU43.
Intel has not observed this event is only enabled while in a sleep state may vary from one logical processor as uncachable and certain instruction fetch timing conditions occur, the system may have the same code page mapped with uncacheable and cacheable memory types at...
Specifications - Page 34
... results should only be Signaled Earlier Than Expected
Problem:
x87 instructions that trigger #MF normally service interrupts before the #MF. Due to launching into the SENTER sleep state. Workaround: If necessary software may be signaled before pending interrupts are set to "1" in a PML4E or PDPTE
On processors supporting Intel® 64 architecture, the PS bit (Page...
Specifications - Page 46
...state properly.
Correctable and Uncorrectable Cache Errors May be Reported Until the First Core C6 Transition
Problem:
On a subset of two things: (1) clear the "load IA32_PERF_GLOBAL_CTRL" VM-
PCIe Port's LTSSM May Not Transition Properly in a core, the VMWRITE instruction may not correctly update the VMCS and the VMREAD instruction may not transition according to the proper...
Specifications - Page 49
... Developer's Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide
There are no new Specification Changes in this Specification Update revision.
49 Specification Update
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