Product Data Sheet
Page 1
... - Two 64-bit operations per JEDEC - Low-latency, high-bandwidth - 144-bit DDR2 SDRAM controller operating at up to 1 Mbyte per L2 cache with double-bit detect and single-bit correct Publication # 43042 Issue Date: May 2007 Revision: 3.00 Advanced Micro Devices Supports up to L1 caches - AMD Athlon™ X2 Dual-Core Processor Product...
... - Two 64-bit operations per JEDEC - Low-latency, high-bandwidth - 144-bit DDR2 SDRAM controller operating at up to 1 Mbyte per L2 cache with double-bit detect and single-bit correct Publication # 43042 Issue Date: May 2007 Revision: 3.00 Advanced Micro Devices Supports up to L1 caches - AMD Athlon™ X2 Dual-Core Processor Product...