User Guide
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... times as large as a 100-MHz cache implementation. 4 AMD-K6™-2E+ Embedded Processor Chapter 1 AMD's cache design innovations include: s An internal 128-Kbyte L2 write-back cache operating at full processor speed. Because the internal L2 cache of the processor and complementing the 64-Kbyte L1 cache, which further enhances overall CPU throughput. s A 4-way set associative backside...
... times as large as a 100-MHz cache implementation. 4 AMD-K6™-2E+ Embedded Processor Chapter 1 AMD's cache design innovations include: s An internal 128-Kbyte L2 write-back cache operating at full processor speed. Because the internal L2 cache of the processor and complementing the 64-Kbyte L1 cache, which further enhances overall CPU throughput. s A 4-way set associative backside...
User Guide
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... RESET is sampled asserted, the CPU input clock is sampled asserted. Driven VID[4:0] are initialized to 01010b when RESET is running, and the core and I/O voltages are supported on the low-power versions only of the DC/DC regulator that these signals, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note...
... RESET is sampled asserted, the CPU input clock is sampled asserted. Driven VID[4:0] are initialized to 01010b when RESET is running, and the core and I/O voltages are supported on the low-power versions only of the DC/DC regulator that these signals, see the Embedded AMD-K6™ Processors BIOS Design Guide Application Note...
User Guide
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... "don't care". 2. A4 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# M/IO# D/C# W/R# CACHE# KEN# 142 Signal Descriptions Chapter 5 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.57 Bus Cycle Definitions Table 23. x means "don't care" Generated by the CPU Generated by System Logic M/IO# 1 1 1 0 0 0 0 1 1 1 1 1 D/C# 0 0 0 0 0 1 1 1 1 1 1 1 W/R# 0 0 0 1 0 0 1 0 0 0 1 1 CACHE# 0 1 x 1 1 1 1 0 1 x 0 1 KEN# 0 x1 1 x x x x 0 x 1 x x Table 24...
... "don't care". 2. A4 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# M/IO# D/C# W/R# CACHE# KEN# 142 Signal Descriptions Chapter 5 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.57 Bus Cycle Definitions Table 23. x means "don't care" Generated by the CPU Generated by System Logic M/IO# 1 1 1 0 0 0 0 1 1 1 1 1 D/C# 0 0 0 0 0 1 1 1 1 1 1 1 W/R# 0 0 0 1 0 0 1 0 0 0 1 1 CACHE# 0 1 x 1 1 1 1 0 1 x 0 1 KEN# 0 x1 1 x x x x 0 x 1 x x Table 24...
User Guide
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...AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 6.2 Dynamic Core Frequency and Core Voltage Control AMD PowerNow! technology state transition is accessed using an SMM handler. These features are implemented in the Voltage ID Output (VIDO) and Internal BF Divisor (IBF) fields of the processor...and the AMD PowerNow! s Afterwards, the EBF[2:0] value can be dynamically controlled through AMD PowerNow! For AMD PowerNow! the EPM Stop Grant state. s This action automatically places the processor into the EPM Stop Grant State and transitions the CPU core ...
...AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 6.2 Dynamic Core Frequency and Core Voltage Control AMD PowerNow! technology state transition is accessed using an SMM handler. These features are implemented in the Voltage ID Output (VIDO) and Internal BF Divisor (IBF) fields of the processor...and the AMD PowerNow! s Afterwards, the EBF[2:0] value can be dynamically controlled through AMD PowerNow! For AMD PowerNow! the EPM Stop Grant state. s This action automatically places the processor into the EPM Stop Grant State and transitions the CPU core ...
User Guide
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...handler. 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Dynamic Core Frequency Control Voltage Identification (VID) Outputs For AMD PowerNow! technology core frequency transitions, ...the BVC field of the core voltage. s This action automatically places the processor into the EPM Stop Grant state and transitions the CPU core voltage and frequency to the SGTC field. Chapter 6 AMD...
...handler. 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Dynamic Core Frequency Control Voltage Identification (VID) Outputs For AMD PowerNow! technology core frequency transitions, ...the BVC field of the core voltage. s This action automatically places the processor into the EPM Stop Grant state and transitions the CPU core voltage and frequency to the SGTC field. Chapter 6 AMD...
User Guide
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... Table 79. AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations Device Type OPN1 Package Type Operating Voltage Case Maximum CPU/Bus Temperature Frequency AMD-K6-2E+/350AUZ 321-pin CPGA 1.4 V-1.6 V (Core) 3.135 V-3.6 V (I/O) 0°C - 85°C 350 MHz/100 MHz AMD-K6-2E+/400ATZ 321-pin CPGA 1.5 V-1.7 V (Core) 3.135 V-3.6 V (I/O) 0°C - 85°C 400 MHz/100 MHz Low Power AMD-K6-2E+/450APZ 321...
... Table 79. AMD-K6™-2E+ Embedded Processor Valid Ordering Part Number Combinations Device Type OPN1 Package Type Operating Voltage Case Maximum CPU/Bus Temperature Frequency AMD-K6-2E+/350AUZ 321-pin CPGA 1.4 V-1.6 V (Core) 3.135 V-3.6 V (I/O) 0°C - 85°C 350 MHz/100 MHz AMD-K6-2E+/400ATZ 321-pin CPGA 1.5 V-1.7 V (Core) 3.135 V-3.6 V (I/O) 0°C - 85°C 400 MHz/100 MHz Low Power AMD-K6-2E+/450APZ 321...