Design Guide
Page 32
.... See "Pipelining Support" on the WCDE bit. "Write to a Cacheable Page" and "Write to all the bits in the appropriate AMD-K6 or AMD-K6E processor data sheet. When all zeros. Any pending write cycle that misses the L1 cache and that addresses memory below this limit is ((27-1)...information on page 69 for more information, see the "Cache Organization" chapter in this field are disallowed). This field, multiplied by means of one of this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are set to 0, ...
.... See "Pipelining Support" on the WCDE bit. "Write to a Cacheable Page" and "Write to all the bits in the appropriate AMD-K6 or AMD-K6E processor data sheet. When all zeros. Any pending write cycle that misses the L1 cache and that addresses memory below this limit is ((27-1)...information on page 69 for more information, see the "Cache Organization" chapter in this field are disallowed). This field, multiplied by means of one of this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are set to 0, ...
Design Guide
Page 33
...is ignored if the value in the WAELIM field is considered a noncacheable region of memory. 23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Write Allocate Enable 15-to prevent write allocates. This memory hole is provided to account for the memory write ...used to a Sector." The WAE15M bit is cacheable by 4 Mbytes, yields 32 Mbytes as the write allocate limit. This value (8), when multiplied by means of these peripherals, the bit should be set to allow write allocates in the memory area between 640 Kbytes and 1 Mbyte (...
...is ignored if the value in the WAELIM field is considered a noncacheable region of memory. 23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Write Allocate Enable 15-to prevent write allocates. This memory hole is provided to account for the memory write ...used to a Sector." The WAE15M bit is cacheable by 4 Mbytes, yields 32 Mbytes as the write allocate limit. This value (8), when multiplied by means of these peripherals, the bit should be set to allow write allocates in the memory area between 640 Kbytes and 1 Mbyte (...
Design Guide
Page 40
... multiplied by 4 Mbytes, defines an upper memory limit. Write Handling Control Register (WHCR) (Models 8/[F:8], 9, and D) Write Allocate Enable Limit Field The WAELIM field is ((210-1) · 4 Mbytes) = 4092 Mbytes. Once the BIOS determines the amount of RAM installed in the appropriate AMD-K6 or AMD-K6E processor data sheet. Figure 6. Preliminary Information Embedded AMD-K6™ Processors BIOS...
... multiplied by 4 Mbytes, defines an upper memory limit. Write Handling Control Register (WHCR) (Models 8/[F:8], 9, and D) Write Allocate Enable Limit Field The WAELIM field is ((210-1) · 4 Mbytes) = 4092 Mbytes. Once the BIOS determines the amount of RAM installed in the appropriate AMD-K6 or AMD-K6E processor data sheet. Figure 6. Preliminary Information Embedded AMD-K6™ Processors BIOS...
Design Guide
Page 68
... the EPM Stop Grant state. If BDC[1:0]=1xb, the IBF[2:0] field is multiplied by 4096 to the IBF[2:0] value upon entering the EPM Stop Grant state. Notes: 1. If VIDC=1, the processor VID[4:0] pins are sampled at RESET. Bus Divisor and Voltage ID Control (...bus divisor control. These bits are initialized to enter the W EPM Stop Grant state internally. This bit controls the mode in processor bus clocks. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 31 12 11 10 9 8 7 54 0 BV SGTC V C I D BDC IBF...
... the EPM Stop Grant state. If BDC[1:0]=1xb, the IBF[2:0] field is multiplied by 4096 to the IBF[2:0] value upon entering the EPM Stop Grant state. Notes: 1. If VIDC=1, the processor VID[4:0] pins are sampled at RESET. Bus Divisor and Voltage ID Control (...bus divisor control. These bits are initialized to enter the W EPM Stop Grant state internally. This bit controls the mode in processor bus clocks. Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 31 12 11 10 9 8 7 54 0 BV SGTC V C I D BDC IBF...