AMD OS1354WBJ4BGHBOX - Third-Generation Opteron 2.2 GHz Processor Support and Manuals
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Optimization Guide - Page 2
...as components in systems intended for use of the AMD hardware, software, or other applications intended to support or sustain life, or in AMD's Standard Terms and Conditions of a preliminary or... set forth in any time without notice. AMD makes no liability with respect to , the implied warranty of merchantability, fitness for identification purposes only and may be of Sale, AMD assumes...
Optimization Guide - Page 6
March 2013 1.1
Description Initial Public Release
52128 Rev. 1.1 March 2013
6
Revision History
Software Optimization Guide for AMD Family 16h Processors
Revision History
Date
Rev.
Optimization Guide - Page 7
... FPU register file. Notational Convention
Instruction mnemonics, micro-instructions, and example code are familiar with the AMD64 instruction set of guidelines for writing efficient code that linear address.
Individual volumes and their order numbers are referred to BIOS and Kernel Developers Guide (BKDG) for AMD Family 16h Models 00h-0Fh Processors (Order # 48751) for more information...
Optimization Guide - Page 8
... Unit
2.1 Features
This topic introduces some of the key features of the processor. Instruction set architecture support includes:
• General-purpose instructions, including support for AMD Family 16h Processors
52128 Rev. 1.1 March 2013
2 Microarchitecture of the Family 16h Processor
An understanding of the terms architecture, microarchitecture, and design implementation is important...
Optimization Guide - Page 9
...) • Carry-less Multiply (CLMUL) instructions • Advanced Encryption Standard (AES) acceleration instructions • Bit Manipulation Instructions (BMI) • Move Big-Endian instruction (MOVBE) • XSAVE / XSAVEOPT • LZCNT / POPCNT • AMD Virtualization™ technology (AMD-V™)
The AMD Family 16h processor does not support the following key features:
•...
Optimization Guide - Page 10
... of macro-ops (the primary units of the Family 16h Processor
Chapter 2 Software Optimization Guide for AMD Family 16h Processors
52128 Rev. 1.1 March 2013
2.2 Instruction Decomposition
The AMD Family 16h processor implements the AMD64 instruction set . Instructions are upper limits, however. Typical Instruction Mappings
Instruction
Macro-ops
MOV reg,[mem]
1
MOV [mem],reg
1
MOV [mem...
Optimization Guide - Page 12
...and unaligned load and store instructions (for example, MOVUPS/ MOVAPS) provide identical performance. Software Optimization Guide for AMD Family 16h Processors
52128 Rev. 1.1 March 2013
2.5.1 L1 Instruction Cache
The AMD Family 16h processor contains a 32-Kbyte, 2-way set associative L1 data cache. Requests that of parity. For a large contiguous block of an error correcting code (ECC).
Optimization Guide - Page 13
... 4-Kbyte page entries and a 2-way set -associative L2 instruction TLB with 256 2-Mbyte page entries....supports 1-Gbyte pages by returning a smashed 2-Mbyte TLB entry.
The minimum branch misprediction penalty is increased. In a nested paging environment, the processor... the instruction or the data side. 52128 Rev. 1.1 March 2013
Software Optimization Guide for AMD Family 16h Processors
2.6...
Optimization Guide - Page 14
...next instruction to support the 32 byte per instruction cache line (64 bytes), for a total of the processor. The...instruction chunk, if located in the same cycle. The BTAC can be predicted in the same 64-byte aligned block. The processor facilities that are predicted not-taken, as up with the branch target address calculator. Software Optimization Guide for AMD Family 16h Processors...
Optimization Guide - Page 15
... in most cases.
The following instruction is evicted, the sparse marker information for out-of-page target prediction. It is recommended to avoid the use of CALL 0h in the shared L2 can be shared with a 4cycle penalty.
52128 Rev. 1.1 March 2013
Software Optimization Guide for AMD Family 16h Processors
2.7.1.4 Out-of-Page Target...
Optimization Guide - Page 16
... to code fewer and longer NOP instructions rather than many short NOP instructions, because while NOP instructions do not...instructions retire from the Decoder and tracked by the Retire Control Unit.
16
Microarchitecture of the Family 16h Processor
Chapter 2 Software Optimization Guide for AMD Family 16h Processors
52128 Rev. 1.1 March 2013
2.7.1.7 Indirect Target Predictor
The processor...
Optimization Guide - Page 17
... penalty is not present in case the code is superior to Reduce Power Consumption
The Family 16h processor includes a loop buffer which can save power by not requiring the full instruction cache lookup. For AMD Family 16h processors use a series of 11-byte NOPs followed by a shorter NOP instruction.
2.7.2.2 Aligning Loops to encoding a JMP around the...
Optimization Guide - Page 18
... Guide ...unit. The scheduler tracks operand availability and dependency information as part of its task of two instructions. Micro-ops can also handle integer multiplies and divides. ...for AMD Family 16h Processors
52128 Rev. 1.1 March 2013
2.8 Instruction Fetch and Decode
The AMD Family 16h processor fetches instructions in two 16byte windows. Each scheduler can perform an instruction block ...
Optimization Guide - Page 19
...52128 Rev. 1.1 March 2013
Software Optimization Guide for 32-bit single precision, 64-bit ...AMD Family 16h processor provides native support for AMD Family 16h Processors
Figure 2. Integer Schedulers and Execution Units
All integer operations can occur. The retire unit handles in-order commit of the Family 16h Processor
19 Generally physical register renames are needed for instructions...
Optimization Guide - Page 20
...the store/convert unit, and
20
Microarchitecture of two over the AMD Family 14h processor. The floating-point unit (FPU) utilizes a coprocessor model. As such it contains its own scheduler, register files, ... / logical units (VALUs) which means that is the pipeline binding. Software Optimization Guide for each pipe.
Figure 3.
The first is dispatched into the integer retire control ...
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