Data Sheet
Page 3
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents Revision Historyxix 1 AMD-K6®-2 Processor 1 1.1 Super7™ Platform Initiative 3 Super7™ Platform Enhancements 3 Super7™ Platform Advantages 4 2 Internal Architecture 5 2.1 Introduction 5 2.2 AMD-K6®-2 Processor Microarchitecture Overview 5 Enhanced RISC86® Microarchitecture 6 2.3 Cache, Instruction Prefetch, and Predecode Bits 9 Cache 9 Prefetching 10 Predecode Bits 10 2.4 Instruction Fetch and Decode 11...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents Revision Historyxix 1 AMD-K6®-2 Processor 1 1.1 Super7™ Platform Initiative 3 Super7™ Platform Enhancements 3 Super7™ Platform Advantages 4 2 Internal Architecture 5 2.1 Introduction 5 2.2 AMD-K6®-2 Processor Microarchitecture Overview 5 Enhanced RISC86® Microarchitecture 6 2.3 Cache, Instruction Prefetch, and Predecode Bits 9 Cache 9 Prefetching 10 Predecode Bits 10 2.4 Instruction Fetch and Decode 11...
Data Sheet
Page 4
... (EFER) -Model 8/[F:8] . 50 Write Handling Control Register (WHCR)-Model 8/[F:8] . . 51 UC/WC Cacheability Control Register (UWCCR)52 Processor State Observability Register (PSOR 53 Page Flush/Invalidate Register (PFIR 53 3.3 Instructions Supported by the AMD-K6®-2 Processor . . . . . 54 4 Signal Descriptions 83 4.1 Signal Terminology 83 4.2 A20M# (Address Bit 20 Mask 85 4.3 A[31:3] (Address Bus 86...
... (EFER) -Model 8/[F:8] . 50 Write Handling Control Register (WHCR)-Model 8/[F:8] . . 51 UC/WC Cacheability Control Register (UWCCR)52 Processor State Observability Register (PSOR 53 Page Flush/Invalidate Register (PFIR 53 3.3 Instructions Supported by the AMD-K6®-2 Processor . . . . . 54 4 Signal Descriptions 83 4.1 Signal Terminology 83 4.2 A20M# (Address Bit 20 Mask 85 4.3 A[31:3] (Address Bus 86...
Data Sheet
Page 5
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents 4.33 LOCK# (Bus Lock 110 4.34 M/IO# (Memory or I/O 111 4.35 NA# (Next Address 112 4.36 NMI (Non-Maskable Interrupt 112 4.37 ...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents 4.33 LOCK# (Bus Lock 110 4.34 M/IO# (Memory or I/O 111 4.35 NA# (Next Address 112 4.36 NMI (Non-Maskable Interrupt 112 4.37 ...
Data Sheet
Page 6
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Hit to Modified Line 152 AHOLD Restriction 154 Bus Backoff (BOFF 156 Locked Cycles 158 ... 6.1 Signals Sampled During the Falling Transition of RESET 173 FLUSH 173 BF[2:0 173 BRDYC 173 6.2 RESET Requirements 174 6.3 State of Processor After RESET 174 Output Signals 174 Registers 174 6.4 State of Processor After INIT 177 7 Cache Organization 179 7.1 MESI States in the Data Cache 180 7.2 Predecode Bits 180 7.3 Cache Operation 181 Cache...
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 AHOLD-Initiated Inquire Hit to Modified Line 152 AHOLD Restriction 154 Bus Backoff (BOFF 156 Locked Cycles 158 ... 6.1 Signals Sampled During the Falling Transition of RESET 173 FLUSH 173 BF[2:0 173 BRDYC 173 6.2 RESET Requirements 174 6.3 State of Processor After RESET 174 Output Signals 174 Registers 174 6.4 State of Processor After INIT 177 7 Cache Organization 179 7.1 MESI States in the Data Cache 180 7.2 Predecode Bits 180 7.3 Cache Operation 181 Cache...
Data Sheet
Page 7
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents WBINVD and INVD 196 Cache-Line Replacement 196 Cache Snooping 198 7.11 Writethrough versus Writeback Coherency States 199 7.12 A20M# Masking of ...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Contents WBINVD and INVD 196 Cache-Line Replacement 196 Cache Snooping 198 7.11 Writethrough versus Writeback Coherency States 199 7.12 A20M# Masking of ...
Data Sheet
Page 8
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 12 Clock Control 243 12.1 Halt State 244 Enter Halt State 244 Exit Halt State 244 12.2 Stop ... Note 265 15.4 I/O Buffer AC and DC Characteristics 265 16 Signal Switching Characteristics 267 16.1 CLK Switching Characteristics 267 16.2 Clock Switching Characteristics for 100-MHz Bus Operation 268 16.3 Clock Switching Characteristics for 66-MHz Bus Operation 268 16.4 Valid Delay, Float, Setup, and Hold Timings 269 viii Contents
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 12 Clock Control 243 12.1 Halt State 244 Enter Halt State 244 Exit Halt State 244 12.2 Stop ... Note 265 15.4 I/O Buffer AC and DC Characteristics 265 16 Signal Switching Characteristics 267 16.1 CLK Switching Characteristics 267 16.2 Clock Switching Characteristics for 100-MHz Bus Operation 268 16.3 Clock Switching Characteristics for 66-MHz Bus Operation 268 16.4 Valid Delay, Float, Setup, and Hold Timings 269 viii Contents
Data Sheet
Page 9
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 16.5 Output Delay Timings for 100-MHz Bus Operation 270 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 272 16.7 Output Delay Timings for 66-MHz Bus Operation 274 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 276 16.9 RESET and...
21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 16.5 Output Delay Timings for 100-MHz Bus Operation 270 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 272 16.7 Output Delay Timings for 66-MHz Bus Operation 274 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 276 16.9 RESET and...
Data Sheet
Page 11
...24. Debug Register DR6 35 Figure 28. Debug Registers DR5 and DR4 35 Figure 29. The Instruction Buffer 11 AMD-K6®-2 Processor Decode Logic 12 AMD-K6®-2 Processor Scheduler 15 Figure 6. FPU Tag Word Register 27 Figure 15. Control Register 3 (CR3 32 Figure 23. Debug... 8-Bit Name Components. . . . . . 22 Figure 8. Floating-Point Register 26 Figure 12. Debug Register DR7 34 Figure 27. AMD-K6®-2 Processor Block Diagram 7 Figure 2. Segment Usage 25 Figure 11. MMX™/3DNow!™ Registers 29 Figure 18. EFLAGS Registers 31 Figure 21. ...
...24. Debug Register DR6 35 Figure 28. Debug Registers DR5 and DR4 35 Figure 29. The Instruction Buffer 11 AMD-K6®-2 Processor Decode Logic 12 AMD-K6®-2 Processor Scheduler 15 Figure 6. FPU Tag Word Register 27 Figure 15. Control Register 3 (CR3 32 Figure 23. Debug... 8-Bit Name Components. . . . . . 22 Figure 8. Floating-Point Register 26 Figure 12. Debug Register DR7 34 Figure 27. AMD-K6®-2 Processor Block Diagram 7 Figure 2. Segment Usage 25 Figure 11. MMX™/3DNow!™ Registers 29 Figure 18. EFLAGS Registers 31 Figure 21. ...
Data Sheet
Page 12
... 141 Figure 61. Basic Locked Operation 159 Figure 70. Stop Grant and Stop Clock Modes, Part 1 168 xii List of Figures AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 37. Page Directory Entry 4-Mbyte Page Table (PDE 45 Figure 43. Page Table Entry... 57. Bus State Machine Diagram 129 Figure 55. Logic Symbol Diagram 84 Figure 53. Application Segment Descriptor 47 Figure 45. Processor State Observability Register (PSOR 53 Figure 51. Locked Operation with BOFF# Intervention 161 Figure 71. Basic HOLD/HLDA Operation 143 Figure...
... 141 Figure 61. Basic Locked Operation 159 Figure 70. Stop Grant and Stop Clock Modes, Part 1 168 xii List of Figures AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 37. Page Directory Entry 4-Mbyte Page Table (PDE 45 Figure 43. Page Table Entry... 57. Bus State Machine Diagram 129 Figure 55. Logic Symbol Diagram 84 Figure 53. Application Segment Descriptor 47 Figure 45. Processor State Observability Register (PSOR 53 Figure 51. Locked Operation with BOFF# Intervention 161 Figure 71. Basic HOLD/HLDA Operation 143 Figure...
Data Sheet
Page 13
...Conditions 190 Figure 82. MSR C000_0085h (Model 8/[F:8 204 Figure 84. TRST# Timing 284 Figure 103. Thermal Model 288 Figure 105. Processor Heat Dissipation Path 290 Figure 107. Write Handling Control Register (WHCR) - Cache Sector Organization 180 Figure 79. External Logic for Supporting... Cacheability Control Register (UWCCR)- Suggested Component Placement 250 Figure 93. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures Figure 75. INIT-Initiated Transition from Protected Mode to Real Mode 171 Figure 77.
...Conditions 190 Figure 82. MSR C000_0085h (Model 8/[F:8 204 Figure 84. TRST# Timing 284 Figure 103. Thermal Model 288 Figure 105. Processor Heat Dissipation Path 290 Figure 107. Write Handling Control Register (WHCR) - Cache Sector Organization 180 Figure 79. External Logic for Supporting... Cacheability Control Register (UWCCR)- Suggested Component Placement 250 Figure 93. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Figures Figure 75. INIT-Initiated Transition from Protected Mode to Real Mode 171 Figure 77.
Data Sheet
Page 14
AMD-K6®-2 Processor Top-Side View 295 Figure 113. Airflow Path in a Dual-Fan System 293 Figure 111. AMD-K6®-2 Processor Pin-Side View 296 Figure 114. 321-Pin Staggered CPGA Package Specification 300 xiv List of Figures Airflow for a Heatsink with Fan 292 Figure 110. Airflow Path in an ATX Form-Factor System 293 Figure 112. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 109.
AMD-K6®-2 Processor Top-Side View 295 Figure 113. Airflow Path in a Dual-Fan System 293 Figure 111. AMD-K6®-2 Processor Pin-Side View 296 Figure 114. 321-Pin Staggered CPGA Package Specification 300 xiv List of Figures Airflow for a Heatsink with Fan 292 Figure 110. Airflow Path in an ATX Form-Factor System 293 Figure 112. AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Figure 109.
Data Sheet
Page 15
...Execution Units . . . . . 16 General-Purpose Registers 22 General-Purpose Register Doubleword, Word, and Byte Names 23 Segment Registers 24 AMD-K6®-2 Processor Model 8/[7:0] MSRs 37 Extended Feature Enable Register (EFER) - Table 5. Table 14. Table 16. Table 20. Table 24. Table 32...11. Table 10. Table 26. Table 29. Table 2. Table 3. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Exceptions and Interrupts 49 AMD-K6®-2 Processor Model 8/[F:8] MSRs 50 Extended Feature Enable Register (EFER)- Table 13. Table 22. Table 35....
...Execution Units . . . . . 16 General-Purpose Registers 22 General-Purpose Register Doubleword, Word, and Byte Names 23 Segment Registers 24 AMD-K6®-2 Processor Model 8/[7:0] MSRs 37 Extended Feature Enable Register (EFER) - Table 5. Table 14. Table 16. Table 20. Table 24. Table 32...11. Table 10. Table 26. Table 29. Table 2. Table 3. 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Exceptions and Interrupts 49 AMD-K6®-2 Processor Model 8/[F:8] MSRs 50 Extended Feature Enable Register (EFER)- Table 13. Table 22. Table 35....
Data Sheet
Page 16
...263 CLK Switching Characteristics for 100-MHz Bus Operation . 268 CLK Switching Characteristics for 66-MHz Bus Operation . . 268 Output Delay Timings for 100-MHz Bus Operation 270 Input Setup and Hold Timings for 100-MHz Bus Operation . 272 Output Delay Timings for 66-MHz Bus Operation 274 Input Setup and...TRST# Timing at 25 MHz 280 Test Signal Timing at 25 MHz 280 Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR 285 xvi List of Tables Table 44. Table 46. Table 50. Table 64. Table 68. Table 52. Table 69. AMD-K6®-2 Processor Data Sheet Preliminary Information...
...263 CLK Switching Characteristics for 100-MHz Bus Operation . 268 CLK Switching Characteristics for 66-MHz Bus Operation . . 268 Output Delay Timings for 100-MHz Bus Operation 270 Input Setup and Hold Timings for 100-MHz Bus Operation . 272 Output Delay Timings for 66-MHz Bus Operation 274 Input Setup and...TRST# Timing at 25 MHz 280 Test Signal Timing at 25 MHz 280 Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR 285 xvi List of Tables Table 44. Table 46. Table 50. Table 64. Table 68. Table 52. Table 69. AMD-K6®-2 Processor Data Sheet Preliminary Information...
Data Sheet
Page 17
Table 73. Table 74. Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR 287 321-Pin Staggered CPGA Package Specification 299 Valid Ordering Part Number Combinations 301 List of Tables xvii 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 72.
Table 73. Table 74. Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR 287 321-Pin Staggered CPGA Package Specification 299 Valid Ordering Part Number Combinations 301 List of Tables xvii 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 72.
Data Sheet
Page 18
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xviii List of Tables
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xviii List of Tables
Data Sheet
Page 19
... Suffixes AHX, AFQ, and AFR," on page 285. Added 533 MHz specifications. F Revised Chapter 7, "Cache Organization" and added Figure 82,"Page Flush/Invalidate Register (PFIR)-MSR C000_0088h," and PFIR's bit descriptions. Revision History xix 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Revision History Date Feb 1999 Feb 1999 Feb 1999...
... Suffixes AHX, AFQ, and AFR," on page 285. Added 533 MHz specifications. F Revised Chapter 7, "Cache Organization" and added Figure 82,"Page Flush/Invalidate Register (PFIR)-MSR C000_0088h," and PFIR's bit descriptions. Revision History xix 21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Revision History Date Feb 1999 Feb 1999 Feb 1999...
Data Sheet
Page 20
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xx Revision History
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 xx Revision History
Data Sheet
Page 21
...-Kbyte instruction cache with additional 20-Kbytes of x86 software. Chapter 1 AMD-K6®-2 Processor 1 Its Super7™ compatible, 321-pin ceramic pin grid array (CPGA) package enables the processor to reduce time-to-market by leveraging today's cost-effective industry-standard ...multimedia performance x Separate multiplier and ALU for superscalar instruction execution s Compatible with Super7™ platform x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support s High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit s High-Performance...
...-Kbyte instruction cache with additional 20-Kbytes of x86 software. Chapter 1 AMD-K6®-2 Processor 1 Its Super7™ compatible, 321-pin ceramic pin grid array (CPGA) package enables the processor to reduce time-to-market by leveraging today's cost-effective industry-standard ...multimedia performance x Separate multiplier and ALU for superscalar instruction execution s Compatible with Super7™ platform x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support s High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit s High-Performance...
Data Sheet
Page 22
... leading-edge performance. technology, new, more powerful hardware and software applications enable a more entertaining and productive PC platform. technology. The AMD-K6-2 processor's 6-issue RISC86 microarchitecture is Super7 and Socket 7-compatible. The AMD-K6-2 processor is a decoupled decode/execution superscalar design that support superscalar operation, out-of real world environments and physics, life-like images and...
... leading-edge performance. technology, new, more powerful hardware and software applications enable a more entertaining and productive PC platform. technology. The AMD-K6-2 processor's 6-issue RISC86 microarchitecture is Super7 and Socket 7-compatible. The AMD-K6-2 processor is a decoupled decode/execution superscalar design that support superscalar operation, out-of real world environments and physics, life-like images and...
Data Sheet
Page 23
...x86 compatibility, and low-cost infrastructure, the AMD-K6-2 is the world's second-leading supplier of performance. Super7™ Platform Enhancements The Super7 platform has the following enhancements: s 100-MHz processor bus-The AMD-K6-2 processor supports a 100-MHz, 800 Mbyte/second frontside bus to provide a...backside L2 and frontside L3 cache-The Super7 platform has the 'headroom' to support higher-performance AMD-K6 processors, with clock speeds scaling to the 100-MHz processor bus protocol, the Super7 initiative includes the introduction of chipsets that have small amounts of 10...
...x86 compatibility, and low-cost infrastructure, the AMD-K6-2 is the world's second-leading supplier of performance. Super7™ Platform Enhancements The Super7 platform has the following enhancements: s 100-MHz processor bus-The AMD-K6-2 processor supports a 100-MHz, 800 Mbyte/second frontside bus to provide a...backside L2 and frontside L3 cache-The Super7 platform has the 'headroom' to support higher-performance AMD-K6 processors, with clock speeds scaling to the 100-MHz processor bus protocol, the Super7 initiative includes the introduction of chipsets that have small amounts of 10...