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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 13.4 Cache Inhibit 263 13.5 L2 Cache and Tag Array Testing 264 13.6 Debug 268 14 Clock Control 275 14.1 ..., and Hold Timings 298 16.5 Output Delay Timings for 100-MHz Bus Operation 298 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 300 16.7 Output Delay Timings for 66-MHz Bus Operation 302 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 304 16.9 RESET and Test Signal Timing 306...
Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 13.4 Cache Inhibit 263 13.5 L2 Cache and Tag Array Testing 264 13.6 Debug 268 14 Clock Control 275 14.1 ..., and Hold Timings 298 16.5 Output Delay Timings for 100-MHz Bus Operation 298 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation 300 16.7 Output Delay Timings for 66-MHz Bus Operation 302 16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 304 16.9 RESET and Test Signal Timing 306...
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... for LowPower AMD-K6™-2E+ Processors Enabled with AMD PowerNow!™ Technology 290 CLK Switching Characteristics for 100-MHz Bus Operation . 296 CLK Switching Characteristics for 66-MHz Bus Operation . . 297 Output Delay Timings for 100-MHz Bus Operation 298 Input Setup and Hold Timings for 100-MHz Bus Operation . 300 Output Delay Timings for 66-MHz Bus Operation...
... for LowPower AMD-K6™-2E+ Processors Enabled with AMD PowerNow!™ Technology 290 CLK Switching Characteristics for 100-MHz Bus Operation . 296 CLK Switching Characteristics for 66-MHz Bus Operation . . 297 Output Delay Timings for 100-MHz Bus Operation 298 Input Setup and Hold Timings for 100-MHz Bus Operation . 300 Output Delay Timings for 66-MHz Bus Operation...
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...Notes: 1. The CLK signal and the internal PLL are still running a suite of Supported Operating Frequencies2 450-200 MHz 400-200 MHz 350-200 MHz 300-200 MHz 400-200 MHz 350-200 MHz 300-200 MHz 350-200 MHz 300-200 MHz Active Power3 8.70-4.90 W 6.90-4.20 W 5.60-3.70 W 4.30-2.95 W 6.90-4.20 W ... automation, networking, and telecommunications. 4. Note that 250-MHz operation is determined for the worst-case instruction sequence or function for the AMD-K6-2E+ processor. 5. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 60. Table 61....
...Notes: 1. The CLK signal and the internal PLL are still running a suite of Supported Operating Frequencies2 450-200 MHz 400-200 MHz 350-200 MHz 300-200 MHz 400-200 MHz 350-200 MHz 300-200 MHz 350-200 MHz 300-200 MHz Active Power3 8.70-4.90 W 6.90-4.20 W 5.60-3.70 W 4.30-2.95 W 6.90-4.20 W ... automation, networking, and telecommunications. 4. Note that 250-MHz operation is determined for the worst-case instruction sequence or function for the AMD-K6-2E+ processor. 5. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 60. Table 61....
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Input Setup and Hold Timings for 100-MHz Bus Operation Table 65. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation Symbol Parameter Description t44 A[31:5] Setup Time t45 A[31:5] Hold Time t461 A20M# Setup Time t471 A20M# Hold Time t48... 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 300 Signal Switching Characteristics Chapter 16
Input Setup and Hold Timings for 100-MHz Bus Operation Table 65. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.6 Input Setup and Hold Timings for 100-MHz Bus Operation Symbol Parameter Description t44 A[31:5] Setup Time t45 A[31:5] Hold Time t461 A20M# Setup Time t471 A20M# Hold Time t48... 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 300 Signal Switching Characteristics Chapter 16
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... on page 300 and Table 67 on page 302, where: v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42 Figure 106. Input Setup and Hold Timing 310 Signal Switching Characteristics Chapter 16 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet...
... on page 300 and Table 67 on page 302, where: v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42 Figure 106. Input Setup and Hold Timing 310 Signal Switching Characteristics Chapter 16 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet...
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Index Numerics 0.18-Micron Process Technology 7 100-MHz Bus clock switching characteristics 296 frontside 1, 8 input setup and hold timings 300 output delay timings 298 Super7 platform support 1, 8 321-Pin Staggered CPGA Package...power management register (EPMR 144 EPM 16-byte I/O block 146 EPM stop grant state 150 I/O base address definition 145 processor state observability register (PSOR 148 SMM handler 145 voltage identification signals 137, 151 AP Signal 98 APCHK# Signal 99 ...
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Index Numerics 0.18-Micron Process Technology 7 100-MHz Bus clock switching characteristics 296 frontside 1, 8 input setup and hold timings 300 output delay timings 298 Super7 platform support 1, 8 321-Pin Staggered CPGA Package...power management register (EPMR 144 EPM 16-byte I/O block 146 EPM stop grant state 150 I/O base address definition 145 processor state observability register (PSOR 148 SMM handler 145 voltage identification signals 137, 151 AP Signal 98 APCHK# Signal 99 ...
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Hold acknowledge cycle 168 acknowledge signal 114, 168-170 HOLD Signal 115 -initiated inquire hit to modified line 172 -initiated inquire hit to ... power-on configuration 199 processor state after INIT 203 processor state after RESET 200 register state 200 RESET requirements 200 signals sampled during RESET 199 Input capacitance 288 leakage current 288 pin float conditions (table 141 pin types (table 140 setup and hold timing 100-MHz bus operation 300 66-MHz bus operation 304 Input...
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Hold acknowledge cycle 168 acknowledge signal 114, 168-170 HOLD Signal 115 -initiated inquire hit to modified line 172 -initiated inquire hit to ... power-on configuration 199 processor state after INIT 203 processor state after RESET 200 register state 200 RESET requirements 200 signals sampled during RESET 199 Input capacitance 288 leakage current 288 pin float conditions (table 141 pin types (table 140 setup and hold timing 100-MHz bus operation 300 66-MHz bus operation 304 Input...
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet HITM 113 HLDA 114 HOLD 115 IGNNE ... 131, 139, 164 cache states (table 226 data cache 223 instruction cache 223 internal cache 223 processor-initiated 223 Software Environment 27 descriptors 59 exceptions (table 62 gates 59 instructions supported 63 interrupts (table...MHz bus operation 296 66-MHz bus operation 297 input setup and hold timings for 100-MHz bus 300 input setup and hold timings for 66-MHz bus 304 output delay timings for 100-MHz bus 298 output delay timings for 66-MHz...
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet HITM 113 HLDA 114 HOLD 115 IGNNE ... 131, 139, 164 cache states (table 226 data cache 223 instruction cache 223 internal cache 223 processor-initiated 223 Software Environment 27 descriptors 59 exceptions (table 62 gates 59 instructions supported 63 interrupts (table...MHz bus operation 296 66-MHz bus operation 297 input setup and hold timings for 100-MHz bus 300 input setup and hold timings for 66-MHz bus 304 output delay timings for 100-MHz bus 298 output delay timings for 66-MHz...